1. Field of the Invention
This invention relates generally to dynamic-type semiconductor memory devices, and more particularly, to an improvement of a scheme for driving a sense amplifier in a dynamic random access memory having a twisted bit line arrangement.
2. Description of the Background Art
As one of semiconductor memory devices, a dynamic-type random access memory (hereinafter, referred to as DRAM) is known. FIG. 1 shows an example of an entire structure of a conventional DRAM.
Referring to FIG. 1, the DRAM includes a memory cell array 1 in which a plurality of memory cells (not shown in FIG. 1) are arranged in a matrix. In order to select one memory cell (in case of 1 bit configuration) of the memory cell array 1, provided are an address buffer 2 for receiving an address A applied from an exterior to generate an internal row address RA and an internal column address CA, an X decoder 3 for decoding the internal row address RA from the address buffer 2 to select one corresponding row in the memory cell array 1, and a Y decoder 4 for decoding the internal column address CA from the address buffer 2 to select one column of the memory cell array 1.
In order to transfer data between a selected memory cell and the exterior of DRAM, provided are a sense amplifier which is activated in response to a sense amplifier activating signal .phi.0 from a sense amplifier activating signal generator 8, for sensing data of memory cells in one row selected by the X decoder 3 for amplification, and an I/O gate for selecting one column in the memory cell array 1 in response to a signal from the Y decoder 4 to connect the selected one to the exterior to the memory. FIG. 1 shows the sense amplifier and the I/O gate as included in one block 7.
In order to define operation timing of DRAM, provided are a RAS buffer 5 which receives a row address strobe signal RAS applied from the exterior for generating an internal signal to apply the same to the address buffer 2, the X decoder 3 and the sense amplifier activating signal generator 8, and a CAS buffer 6 which generates an internal control signal (a signal for controlling column selecting operation) in response to the column address strobe signal CAS for applying the same to the address buffer 2 and the Y decoder 4.
The address A from the exterior to the address buffer 2 has a row address and a column address time division multiplexed. The address buffer 2 generates an internal row address RA and an internal column address CA after accepting the internal address A as a row address and a column address in response to each internal control signal from the RAS buffer 5 and the CAS buffer 6.
FIG. 2 shows an example of a detailed structure of the memory cell array 1, the sense amplifier and I/O gate block 7 shown in FIG. 1.
Referring to FIG. 2, memory cells MC are arranged in matrix of rows and columns. Bit lines each for connecting a column of the memory cell array 1 constitute a folded bit line scheme wherein two bit lines are disposed in pair. More specifically, bit lines BL0 and BL0 connect one column of the memory cell array, and respective bit lines BL1, BL1 and BL2, BL2, and BLm, BLm select one column of the memory cell array.
Word lines WL1, WL2, . . . , each connecting one row of the memory cell array 1 are provided so as to intersect with each of bit lines BL0 - BLm.
Sense amplifiers 10 - 1.about.10 - n are provided on each of bit line pairs BL0, BL0, . . . , and BLm, BLm, which are activated in response to a sense amplifier activating signal .phi.0 for sensing potentials of a corresponding bit line pair for amplification.
Precharging-equalizing circuits 15 - 1.about.15 - n are provided on each of bit line pairs BL0, BL0, . . . and BLm, BLm for precharging and equalizing each bit line pair to a predetermined potential (usually, half an operation power supply potential Vcc/2).
Furthermore, each of column selecting switches T0, T0', T1, T1', T2, T2', . . . , Tm, Tm' is respectively provided corresponding to each bit line for connecting one column of the memory cell array 1 to data input/output buses I/O, I/O in response to a column selecting signal from the Y decoder 4.
A memory cell MC is disposed at an intersection of each word line and one bit line of a bit line pair.
Parasitic capacitance C.sub.M inevitably exists between adjacent bit line pairs. The parasitic capacitance C.sub.M becomes large as a pitch or space between bit lines is made smaller concomitantly with the high integration of DRAM.
Now, brief description of operation will be made, taking an example of that in data reading. Initially, DRAM is in a stand-by state, and a row address strobe signal RAS is at "H" level. Accordingly, each of precharging/equalizing circuits 15 - 1.about.15 - n is in active state to precharge a corresponding bit line pair to a predetermined precharge potential Vp and hold the same.
When the row address strobe signal RAS drops to the "L" level, a memory cycle starts, thereby causing the address buffer 2 to accept an external address A for applying as an internal row address RA to the X decoder 3. The X decoder 3 decodes the internal row address RA and selects a single word line (e.g. a word line WL1) in the memory cell array 1, so that stored information in the memory cells MC connected to the selected word line (WL 1) is transferred onto a corresponding bit line. Then, each of the sense amplifiers 10 - 1.about.10 - n is activated by the sense amplifier activating signal .phi.0 from the sense amplifier activating signal generator 8, so that potentials on each bit line pair are sensed to be differentially amplified. Then, in response to an internal control signal from the CAS buffer 6, the address buffer 2 generates an internal column address CA to be applied to the Y decoder 4. The Y decoder 4 decodes the internal column address CA, and applies a column selecting signal to transfer gates T0 - Tm' for selecting a corresponding column, so that a pair of column selecting switches enters an on state and the selected bit line pair is connected to the data input/output buses I/O and I/O, and then the selected memory cell data is read out to the exterior.
Data reading is performed in the above operation, wherein each of sense amplifiers 10 - 1.about.10 - n (hereinafter, as a representative, a sense amplifier is shown as a reference numeral 10) differentially amplifies a very small potential difference on a corresponding bit line pair. If a DRAM is more integrated, a parasitic capacitance C.sub.M between bit line pairs becomes large, so that a read potential between adjacent bit lines affects each other by means of capacitive coupling. Therefore, a problem arises that the sense amplifier 10 can not correctly sense and amplify a potential difference between a corresponding bit line pair. The situation of this will be explained in more detail in the following.
FIGS. 3A to 3D show change of a potential of each bit line pair during the operation of a sense amplifier. FIGS. 3A to 3D also show effects on reference potentials of a bit line pair BL1 and BL1 exerted by bit line pairs BL0, BL0 and BL2, BL2. In the following, referring to FIGS. 3A to 3D, potential changes of bit lines due to capacitive coupling between adjacent bit line pairs at the time of operation of a sense amplifier will be described.
First, referring to FIG. 3A, an operation will be described wherein potentials of the logical low ("L") level are read out onto both of a bit line BL0 and a bit line BL2. When a potential of a selected word line (for example, a word line WL1 in FIG. 2) rises at the time of t0, information of a memory cell MC connected to the selected word line is transferred to the bit lines BL0 and BL2. At this time, the potentials of the bit lines BL0 and BL2 do not deviate and remain at the reference potential. Accordingly, a potential of a bit line BL1 adjacent to the bit line BL0 does not change and remains at the precharge potential V.sub.p. On the other hand, the potential change .DELTA.V1 of the bit line BL2 is transferred to a bit line BL1 adjacent to the bit line BL2 by means of capacitive coupling, so that the reference potential of the BL1 drops by .DELTA.V1'. At the time t1, a sense amplifier 10 is activated, thereby starting discharging a bit line of a lower potential of a bit line pair, so that the potential change .DELTA.V2-1 of the bit line BL2 is transferred to the bit line BL1 by means of capacitive coupling and the reference potential (precharge potential) of the bit line BL1 further drops by .DELTA.V2'- 1. When the sense amplifier further operates at the time t2, and bit lines of higher potential are charged to the operation power supply potential Vcc level, the potentials of the bit lines BL0 and BL2 rise to the power supply potential Vcc. Accordingly, the potential of the bit line BL1 rises by means of capacitive coupling by .DELTA.V3'-1 according to the potential change .DELTA.V3'- 1 of the bit line BL0.
Referring to FIG. 3B, described is a deviation of the reference potentials (precharge potential) of bit lines BL1 and BL1 when potentials of the logical high "H" level are read out onto the bit lines BL0, BL2. First, when a potential of a selected word line rises at the time t0, data of respective memory cells connected to the selected word line are transferred to the bit lines BL0 and BL2, thereby causing the potentials of the bit lines BL0 and BL2 to rise by .DELTA.V1. Due to the potential rise .DELTA.V1 of the bit line BL2, a potential of the bit line BL1 rises by .DELTA.V1' by means of capacitive coupling. When the sense amplifier 10 is activated at the time t1, bit lines of lower potentials are discharged to the ground potential, thereby causing a potential of the bit line BL0 to drop to 0V, and causing the potential drop to the bit line BL1 by means of capacitive coupling, so that a potential of the bit line BL1 drops by .DELTA.V2'- 2. When at the time t2, a further operation of the sense amplifier causes bit line potentials of higher potential to rise to the power supply potential Vcc level, the potentials of the bit lines BL0 and BL2 further rise by .DELTA.V3 - 2. The potential rise .DELTA.V3 - 2 of the bit line BL2 is transferred to the bit line BL1 by means of capacitive coupling, so that the reference voltage of the bit line BL1 further rises by .DELTA.V3'- 2.
With reference to FIG. 3C, described is an operation wherein a potential of the "L" level is transferred to the bit line BL0 and a potential of the "H" level is transferred to the bit line BL2. At the time t0, when a potential of a selected word line rises, a potential of the bit line BL2 rises by .DELTA.V1, while a potential of the bit line BL0 drops by .DELTA.V1. The potential drop .DELTA.V1 of the bit line BL2 is transferred to the bit line BL1 by means of capacitive coupling, so that the reference potential of the bit line BL1 rises by .DELTA.V1'. At the time t1, when the sense amplifier 10 is activated, bit lines of lower potential are discharged. At this time, since bit lines to be discharged are bit lines BL0 and BL2, the potentials do not rise due to capacitive coupling to the bit lines BL1 and BL1, and reference potentials of the bit lines BL1 and BL1 remain the same as that of the time t1 when at the time t2, a further operation of the sense amplifier causes bit lines of higher potential to charge, a potential of the BL0 rises by .DELTA.V3 - 1, and the potential of the bit line BL2 rises by .DELTA.V3 -2. As a result, the reference voltage of the bit line BL1 rises by .DELTA.V3'-1, while the reference potential of the bit line BL1 rises by .DELTA.V3'- 2.
Operation will be described with reference to the FIG. 3D wherein a potential of the "H" level is transferred to the bit line BL0 and a potential of the "0" level to the bit line BL2. At the time t0, when a selected word line is activated, a read potential .DELTA.V1 is transferred to the bit line BL0 and BL2. As a result, the reference potential of the bit line BL1 drops by .DELTA.V1'. At the time t1, when the sense amplifier is activated, the bit lines BL0 and BL2 are discharged to the ground potential. The potential drops .DELTA.V2 - 1 of the bit line BL2 is transferred to the bit line BL1 by means of capacitive coupling, thereby causing the reference potential of the bit line BL1 to further drop by .DELTA.V2'-2. The potential drop .DELTA.V2'-2 of the bit line BL0 is transferred to the bit line BL1 by means of capacitive coupling, thereby causing the reference potential of the bit line BL1 to drop by .DELTA.V2'- 2. At the time t2, operation of the sense amplifier causes potentials of the bit lines BL0 and BL2 of higher potential to start rising up to the power supply potential Vcc level. The potential rise of the bit lines BL0 and BL2 after the time t2 does not affect the potentials of the bit lines BL1 and BL1.
As described in the foregoing, as the degree of integration of a semiconductor memory device DRAM is increased, a space between bit lines becomes narrower, and capacitance value of parasitic capacitance C.sub.M becomes larger. In this case, if potential changes caused by a coupling capacitance between adjacent bit lines are in the same phase, adverse effect on a sensing operation can be avoided, but when a noise occurs in the opposite phase, correct data reading can not be performed. More specifically, since the sense amplifier differentially amplifies a potential difference of a bit line pair, if noise of the same phase appears on a bit line pair, it is possible to cancel that noise and detect correctly the potential of the bit line pair. However, as shown in FIG. 3A and FIG. 3B, if noise of opposite phase occurs on a bit line pair, sometimes it will be impossible to read data correctly due to reduction in a potential difference of a bit line pair or due to inverse of readout data, caused by the noise.
A twisted bit line arrangement as shown in FIG. 4 is proposed in order to prevent operation of erroneous data reading due to capacitive coupling noise in such a highly integrated DRAM as the above. In FIG. 4, although the same reference numerals are given to the corresponding portions in FIG. 2, a bit line pair having crossing portion in the central portion is disposed every other pair. More specifically, while in FIG. 4, a bit line pair BL1 and BL1, and bit line pair BLm and BLm are non-twisted bit line pair without crossing portion, bit line pair BL0 and BL0, and bit line pair BL2 and BL2 construct a twisted bit line pair arrangement having crossing portion in the center. In this case, for example, value of coupling capacitance of the bit line BL1 is reduced due to capacitive coupling to the respective bit lines BL0 and BL0 through coupling capacitance C.sub.M /2, and noise by means of the capacitive coupling to the adjacent bit lines BL0 and BL0 becomes opposite phase, while noise of the same phase is transferred from the bit line BL1 to bit line BL0 and BL0, thereby intending to reduce noise through coupling capacitance. FIGS. 5A to 5D show a diagram illustrating potential change in sensing operation of DRAM of a twisted bit line arrangement shown in FIG. 4.
FIG. 5A shows changes of reference potentials of the bit lines BL1 and BL1 when potentials of the "L" level are transferred to the bit lines BL0 and BL2, FIG. 5B shows changes of reference potentials of the bit lines BL1 and BL1 when potentials of the "H" level are transferred to the bit lines BL0 and BL2, FIG. 5C shows changes of reference potentials of the bit lines BL1 and BL1 when potentials of the "H" level are transferred to the bit line BL2, and FIG. 5D shows changes of reference potentials of the bit lines BL1 and BL1 when a potential of the "H" level is transferred to the bit line BL0 and that of the "L" level to the bit line BL2.
As shown in FIGS. 5A to 5D, all the potential changes of the bit lines .DELTA.V2'- 2, and .DELTA.V3"- 2 caused by capacitive coupling of adjacent bit line pairs occur in the same phase, and the amount of potential changes due to capacitive coupling is smaller than that in a non-twisted bit line structure. Accordingly, even if DRAM is more highly integrated and a pitch between bit lines is made smaller, it is possible to reduce noise caused by capacitive coupling and to make noise through capacitive coupling into the same phase on each bit line pair by employing the above twisted bit line structure, so that it will be possible to prevent erroneous detection of data in the sensing operation.
As in the foregoing, in a highly integrated DRAM, a twisted bit line structure makes it possible to reduce the amount of potential changes of bit lines caused by capacitive coupling between adjacent bit line pairs and to make capacitive coupling noise into noise of the same phase, and thus erroneous reading of data can be prevented. However, as DRAM is more highly integrated to have larger capacity, the number of memory cells connected to a single word line is increased. More specifically, for example, in the case of DRAM of 1M bit, 1024 memory cells are connected to a single word line. Since a single sense amplifier is provided to a single column, 1024 sense amplifiers are needed in the case of DRAM of 1M bit. In this case, since 1024 sense amplifiers are all to be operated simultaneously, potentials of the bit lines are charged or discharged through the sense amplifiers. As a result, peak current flowing through sense amplifiers in operation is increased, so that a large current leakage flows into a substrate to generate substrate current (hole current caused by impact ion and the like), and substrate potential deviates, resulting in malfunction of any circuit of DRAM in some case.
More specifically, a constant bias potential is usually provided to a substrate, so that a threshold voltage of MOSFET (insulated gate type field effect transistor) formed on a semiconductor substrate is stabilized, parasitic capacitance (junction capacitance) is reduced, and occurrence of parasitic FET caused between interconnection lines and the substrate is prevented, thereby stabilizing operation of each circuit. However, as in the foregoing, if many sense amplifiers operate simultaneously and large peak current flows through a substrate, not only the operation power supply potential deviates but also potential of the substrate deviates due to hole current flowing into the substrate, thereby causing malfunction of each circuit and making the correct data reading impossible.
Reduction of peak current has been tried by dividing a memory cell array into blocks, activating only a block comprising a selected memory cell, and operating only sense amplifiers included in the activated block. However, even in this scheme, the more the memory cells included in one block, the more the sense amplifiers operate simultaneously, which results in a large peak current flow.